// $Module: reg_ive_hist $
// $RegisterBank Version: V 1.0.00 $
// $Author:  $
// $Date: Wed, 15 Dec 2021 10:10:49 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  IVE_HIST_REG_0  0x0
#define  IVE_HIST_REG_1  0x4
#define  IVE_HIST_REG_2  0x8
#define  IVE_HIST_REG_IVE_HIST_ENABLE   0x0
#define  IVE_HIST_REG_IVE_HIST_ENABLE_OFFSET 0
#define  IVE_HIST_REG_IVE_HIST_ENABLE_MASK   0x1
#define  IVE_HIST_REG_IVE_HIST_ENABLE_BITS   0x1
#define  IVE_HIST_REG_SHDW_SEL   0x0
#define  IVE_HIST_REG_SHDW_SEL_OFFSET 1
#define  IVE_HIST_REG_SHDW_SEL_MASK   0x2
#define  IVE_HIST_REG_SHDW_SEL_BITS   0x1
#define  IVE_HIST_REG_SOFTRST   0x0
#define  IVE_HIST_REG_SOFTRST_OFFSET 2
#define  IVE_HIST_REG_SOFTRST_MASK   0x4
#define  IVE_HIST_REG_SOFTRST_BITS   0x1
#define  IVE_HIST_REG_IVE_HIST_TILE_NM   0x0
#define  IVE_HIST_REG_IVE_HIST_TILE_NM_OFFSET 4
#define  IVE_HIST_REG_IVE_HIST_TILE_NM_MASK   0xf0
#define  IVE_HIST_REG_IVE_HIST_TILE_NM_BITS   0x4
#define  IVE_HIST_REG_FORCE_CLK_ENABLE   0x0
#define  IVE_HIST_REG_FORCE_CLK_ENABLE_OFFSET 8
#define  IVE_HIST_REG_FORCE_CLK_ENABLE_MASK   0x100
#define  IVE_HIST_REG_FORCE_CLK_ENABLE_BITS   0x1
#define  IVE_HIST_REG_FORCE_DMA_DISABLE   0x0
#define  IVE_HIST_REG_FORCE_DMA_DISABLE_OFFSET 9
#define  IVE_HIST_REG_FORCE_DMA_DISABLE_MASK   0x200
#define  IVE_HIST_REG_FORCE_DMA_DISABLE_BITS   0x1
#define  IVE_HIST_REG_IVE_HIST_STRIDE   0x4
#define  IVE_HIST_REG_IVE_HIST_STRIDE_OFFSET 0
#define  IVE_HIST_REG_IVE_HIST_STRIDE_MASK   0xffff
#define  IVE_HIST_REG_IVE_HIST_STRIDE_BITS   0x10
#define  IVE_HIST_REG_IVE_HIST_MEM_ADDR   0x8
#define  IVE_HIST_REG_IVE_HIST_MEM_ADDR_OFFSET 0
#define  IVE_HIST_REG_IVE_HIST_MEM_ADDR_MASK   0xffffffff
#define  IVE_HIST_REG_IVE_HIST_MEM_ADDR_BITS   0x20
